Improvement of the performance of LSIs by scaling becomes more difficult as the process generation proceeds. Further, a rapid increase in the manufacturing cost becomes a serious problem as the LSI is miniaturized. In such a condition, attempts are actively made to enhance the performance of LSIs by stacking semiconductor chips by use of chip-to-chip electrodes such as micro-bumps, through-silicon vias (TSVs) and the like. Among them, the chip structure which is made by stacking a memory chip on a processor chip is considered desirable and is positively developed.
When data is transferred between the processor chip and the memory chip, it is necessary to transfer a control signal, address, input/output data and the like from the bus of the processor chip to the bus of the memory chip via the chip-to-chip electrodes. That is, it is necessary to provide a plurality of chip-to-chip electrodes corresponding in number to the number of signals such as a control signal, address signal, data signal and the like. Generally, electrode pitch is approximately 100 to 1000 times larger than the interconnect pitch of the buses.
Therefore, since a large number of electrodes corresponding in number to the number of signals are used when the processor chip and the memory chip are stacked, a problem that the chip area is increased occurs. Further, a long interconnect is required to connect the bus to the chip-to-chip electrode and a problem that the signal is delayed and the power consumption is increased due to the long interconnect occurs.